Method for parallel testing of semiconductor devices

ABSTRACT

A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.

BACKGROUND OF THE INVENTION

This invention relates in general to integrated circuit testing, andmore particularly to parallel testing of semiconductor memory circuits.

Semiconductor memories, also known as dynamic random access memories(DRAM) or static random access memories (SRAM), have become increasinglyimportant components in many electronic circuits. To insure highquality, the semiconductor memories must be extensively tested before amanufacturer ships product to a customer. Recently, semiconductormemories have increased dramatically in complexity so that one to fourmillion memory cells can be formed in a single integrated circuit.Testing such complex circuits requires a significant amount of time inthe range of five to ten minutes per circuit or more.

To minimize test time, testers have been developed which can test aplurality of chips in parallel. These testers allow up to 32 memorycircuits to be tested in essentially the same time as a single memorycircuit. Parallel memory testers have been used to test packagedsemiconductor memories for some time.

A large portion of the cost of manufacturing an integrated circuit isincurred in packaging the integrated circuit. It is desirable to packageonly functional integrated circuits so that packaging cost is notincurred on devices which will be thrown away. Testing semiconductormemories in chip or wafer form, before packaging, requires as much timeas testing after packaging. Due to the close spacing of contact padswhich are formed on the semiconductor memories, however, it has beendifficult to make contact to enough integrated circuits to make paralleltesting practical. When testing integrated circuits in chip or waferform, the contact pads are usually coupled to a tester by probe needleswhich are mounted on a probe card or similar device. The probe needlesmust be aligned to the pattern of contact pads on the integrated circuitand must remain aligned through many test cycles. This alignment problembecomes more difficult as more probe needles are added to the probecard. This problem has made it virtually impossible to test more thanfour integrated circuits in parallel in chip or wafer form.

In addition to the alignment problem with probe needles, anynon-planarity in the semiconductor wafer created difficulty incontacting all of the contact pads. As attempts were made to place moreneedles in contact with the wafer, this co-planarity problem becomesmore acute. Although probe cards have been made with probe needles whichcan test up to four semiconductor memories in parallel, due to thedifficulties set out above operating speed is low, maintenance cost ishigh and reliability is compromised.

Access time is a figure of merit for semiconductor memories. Memoriesmust be tested at high speed and sorted into groups having similaraccess times. Conventional probe needle testing does not allow this highspeed testing, and so the sorting operation could only be done after thedevices were packaged. This made it difficult to predict availability ofa memory of a particular access time group until the very end of theassembly process. It is advantageous to know the access time of a memoryas early as possible, preferably when the memories are still in waferform.

Recently, membrane probe card technology has been used to probeintegrated circuit chips with closely spaced contact pads. Thistechnology was described by B. Leslie and F. Matta in "Membrane ProbeCard Technology (The Future for High Performance Wafer Test)," presentedat the 1988 IEEE International Test Conference. This technology has beenused to replace probe needles with probe bumps which are formed on aflexible membrane. However, since chips were still tested individually,little improvement was realized in process cycle time.

Accordingly, it is an object of the present invention to provide amethod for testing integrated circuits in parallel prior to packaging.

It is another object of the present invention to provide a method oftesting semiconductor memories without probe needles.

It is a further object of the present invention to provide a method oftesting integrated circuits which compensates for co-planarity problems.

It is a further object of the present invention to provide a method oftesting semiconductor memories with higher throughput and lower cost.

Another object of the present invention is to provide a method oftesting semiconductor memories which allows high speed testing to becompleted in wafer form.

It is another object of the present invention to provide a method oftesting semiconductor memories which takes advantage of testers whichare capable of testing a plurality of memories in parallel.

SUMMARY OF THE INVENTION

These and other objects of the present invention are achieved by testingintegrated circuits using a tester which is capable of testing aplurality of semiconductor memory chips in parallel, and a membrane testhead having a plurality of probes thereon. The probes are coupled to thetester and to a plurality of contact pads which are formed on thesemiconductor memory chips. In this manner, a plurality of semiconductormemories can be tested in wafer form. Alternatively, individualsemiconductor memory chips can be mounted on a receiver plate and testedindividually or in parallel by moving the receiver plate so that thecontact pads couple to the probes.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a portion of a prior art membrane probe card;

FIG. 2 illustrates the alignment of a membrane probe of the presentinvention to a plurality of memory chips;

FIGS. 3 and 4 illustrate the process of contacting a plurality of memorychips using the membrane probe of FIG. 2; and

FIG. 5 illustrates a receiver plate of the present invention.

DETAILED DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a perspective view of a portion of a prior artmembrane probe used in the present invention. Structural details of themembrane probe can be found in "Membrane Probe Card Technology (TheFuture for High Performance Wafer Test)" by Brian Leslie and FaridMatta, 1988 International Test Conference, pp. 601-607. Membrane 16comprises a flexible printed circuit board material. On a bottom surfaceof membrane 16, a plurality of probe bumps 17 are formed which extendseveral mils below the surface of membrane 16. A conductive ground plane22 is also formed on the bottom surface of membrane 16. On a top surfaceof membrane 16, microstrip transmission lines 21 are formed to coupleprobe bump 17 to a tester (not shown). Contact is made to microstriptransmission lines 21 at an edge of membrane 16, as is commonly donewith printed circuit boards. Conventional printed circuit boardtechniques are used to form probe bumps 17, microstrip transmissionlines 21, and conductive ground plane 22. Optionally, ground lines 15may be formed in between microstrip transmission lines 21 to improvesignal integrity.

FIG. 2 illustrates a typical mounting arrangement for membrane 16.Membrane 16 is mounted to support 19 so that bumps 17 extend away fromsupport 19. Support 19 provides mechanical support for membrane 16 andconveniently allows pressure to be applied to membrane 16 from the topside. Pressure may be applied by a weight, air pressure, water pressure,or the like. Membrane 16 will stretch and distend like a balloon. Thispressure bends membrane 16 and forces probe bumps 17 to extend away fromsupport 19. It should be understood that support 19 may be any shapenecessary to adapt to other equipment used in testing, such as probemachines. Integrated circuit chips 12 are placed in proximity withmembrane 16 and probe bumps 17 are aligned to contact pads 13 formed onintegrated circuit chips 12. Preferably, integrated circuit chips 12 aresemiconductor memory chips, but any circuit which is compatible withparallel testing may be used. One probe bump 17 is provided for eachcontact pad 13 on memory chips 12 to be tested. Memory chips 12 and/orthe membrane probe are moved toward each other so as to couple probebumps 17 to contact pads 13. It will be understood that only sixintegrated circuit chips 12 are shown for ease of illustration; however,many more chips 12 are intended to be tested in parallel.

FIGS. 3 and 4 illustrate the contact process as probe bump 17 andcontact pads 13 are moved toward each other. Memory chip 12a illustratedin FIG. 3 suffers from a severe co-planarity problem in that contactpads 13 are vertically misaligned from each other. Additionally, contactpads 13 on memory chip 12b are vertically misaligned from those on chip12a. Co-planarity problems within a chip, as well as from chip to chipare common. Usually, each memory chip 12 may have 10-30 contact pads 13.FIG. 4 illustrates how flexible membrane 16 conforms to theirregularities presented by memory chips 12a and 12b. Membrane 16 bendsto conform to the irregularity so that a constant pressure is applied toeach of the contact pads 13 on chips 12a and 12b by probe bumps 17. Ithas been found that by using a membrane probe, hundreds of connectionscan be made over a large area. In particular, connections can be made tomultiple chips simultaneously, whether or not the chips are in waferform or chip form. In this manner, reliable non-damaging contact is madeto contact pads 13.

Improved contact may be obtained if probe bumps 17 are irregularlyshaped instead of round. It is believed that the irregular shape willencourage a scrubbing motion as probe bumps 17 rub against contact pads13. The scrubbing motion will break through any metal oxide which may beon the surfaces of probe bumps 17 or contact pads 13. Probe bumps 17 canbe etched to have a rounded trapezoidal shape which would accomplishthis scrubbing motion.

Microstrip transmission lines 21 on the upper surface of membrane 16allow high speed signals to be transmitted to and from memory chips 12with minimal signal distortion. This feature allows high speed testingof memory chips 12 so that the chips can be sorted for access timebefore assembly. This allows manufacturers to build only product whichis in demand, and to predict lead times on product with improvedaccuracy.

The plurality of chips 12 shown in FIG. 2 may be either in wafer form ormounted on receiving plate 31 as illustrated in FIG. 5. In a preferredembodiment, the present invention is practiced by dicing memory chips 12from a semiconductor wafer on which they are formed. Sawing, scribing,or the like may be used to separate semiconductor chips 12 from thewafer on which they are formed. Conventional pick and place equipment isthen used to remove the diced chips and accurately place them onreceiver plate 31 illustrated in FIG. 5. Receiver plate 31 has aplurality of wells machined or etched into a top surface, each wellhaving a vacuum port 32 formed therein. The wells are large enough sothat chips 12 can easily be placed in and removed from the wells, butnot so large as to allow significant movement by chips 12 once they areplaced in the well. Three wells are shown empty in FIG. 5 to illustratevacuum ports 32. Preferably, about ten percent of the thickness ofmemory chip 12, or about 1-2 mils, extends above the well. Vacuum ports32 are sized to hold memory chips 12 in place after they have beenplaced on receiver plate 31. Receiver plate 31 may be made of ceramic,metal, or the like. In a preferred embodiment, receiver plate 31 canhold up to thirty-two memory chips.

Membrane probe 16 as shown in FIG. 2 is then placed in contact withcontact pads on semiconductor chips 12 as described hereinbefore. Memorychips 12 are then tested in parallel, greatly increasing the throughputof the probe test operation. Once testing is complete, receiver plate 31is pulled away from the membrane probe and pick and place equipment isonce again used to remove die which have passed the test from receiverplate 31. At this point, memory chips 12 can be mounted directly on leadframes for further packaging, or stored for future assembly.

It is useful to create a map of memory chips 12 which have passedtesting so that good die can be sorted from bad die, or so that diehaving similar access times can be grouped together. This map can be aphysical map, recorded on paper, or a computer map. Alternatively,memory chips 12 are inked after testing to indicate test results.Mapping or inking is particularly necessary when testing in wafer form,but may be useful when using receiver plate 31 also.

By now, it should be appreciated that a method for testing semiconductormemories in chip or wafer form having improved throughput is provided.By testing memory chips in parallel, equipment utilization is improvedand assembly yields are improved by assembling only chips which passtesting. By using membrane probe technology to test multiple die inparallel, manufacturing and assembly costs are greatly reduced.

I claim:
 1. A method of testing a plurality of semiconductor memorychips which are separated from a semiconductor wafer in which they wereformed in parallel comprising the steps of: providing a tester which iscapable of parallel testing memory devices; providing a flexiblemembrane having a plurality of probe bumps which are coupled to thetester; placing the individual memory chips on a receiver plate, whereinthe receiver plate has a plurality of vacuum ports for holding thememory chips; testing access time of the plurality of memory chips inparallel; and storing information relating to location of memory chipswhich pass the test.
 2. The method of claim 1 further comprising thesteps of: removing the chips which pass the test from the receiver plateand mounting them on a leadframe.
 3. The method of claim 1 wherein eachof the probe bumps on the flexible membrane is coupled to the tester bya transmission line formed on the flexible membrane.
 4. A method fortesting a plurality of integrated circuits which are separated from asemiconductor wafer in which they were formed, wherein each of theintegrated circuits has a plurality of contact pads for electricalconnection to the integrated circuit, the method comprising the stepsof: providing a receiver plate having a vacuum port for each of theplurality of integrated circuits, wherein the vacuum port is sized tohold one of the integrated circuits; providing a well in the receiverplate surrounding each of the vacuum ports, wherein the well is sized toprevent substantial movement of the integrated circuit; providing amembrane probe having a plurality of probe bumps formed on one side of aflexible membrane, wherein the probe bumps are electrically coupled to atester; placing each of the integrated circuits individually on thereceiver plate covering one vacuum port; applying a vacuum to each ofthe vacuum ports; moving the receiver plate and/or the membrane probe sothat the probe bumps couple to each of the plurality of contact pads ofthe plurality of integrated circuits; and testing the plurality ofintegrated circuits.
 5. The method of claim 4 wherein the plurality ofintegrated circuits comprise semiconductor memory circuits.
 6. Themethod of claim 4 wherein the tester is capable of testing a pluralityof memory circuits in parallel.
 7. The method of claim 4 wherein themembrane probe further comprises a ground plane formed on the same sideof the flexible membrane as the probe bumps.
 8. The method of claim 7wherein the probe bumps are coupled to the tester by striplineconductors formed on a side of the flexible membrane opposite the probebumps.